The present disclosure relates to a semiconductor device and a method for producing the same, and more particularly to a semiconductor device of a three-dimensional structure including fin-shaped semiconductor regions on a substrate and a method for producing the same.
In recent years, demands for miniaturizing semiconductor devices have been increasing along with the increase in the degree of integration, functionality and speed thereof. In view of this, various device structures have been proposed in the art, aiming at the reduction in the area of the substrate taken up by transistors. Among others, attention has been drawn to field effect transistors having a fin-shaped structure. A field effect transistors having the fin-shaped structure is commonly called a fin-shaped FET (field effect transistor), and has an active region including thin wall (fin)-like semiconductor regions perpendicular to the principle plane of the substrate. In a fin-shaped FET, the side surface of the semiconductor region can be used as a channel surface, whereby it is possible to reduce the area on the substrate taken up by the transistor (see, for example, Patent Document 1 and Non-Patent Document 1).
FIGS. 27A-27D show a structure of a conventional fin-shaped FET, wherein FIG. 27A is a plan view, FIG. 27B is a cross-sectional view taken along line A-A in FIG. 27A, FIG. 27C is a cross-sectional view taken along line B-B in FIG. 27A, and FIG. 27D is a cross-sectional view taken along line C-C in FIG. 27A.
As shown in FIGS. 27A-27D, a conventional fin-shaped FET includes a supporting substrate 101 made of silicon, an insulating layer 102 made of silicon oxide formed on the supporting substrate 101, semiconductor regions 103a to 103d each formed into a fin shape on the insulating layer 102 (hereinafter referred to as the “fin-shaped semiconductor regions”), a gate electrode 105 formed on the fin-shaped semiconductor regions 103a to 103d via gate insulating films 104a to 104d, insulative sidewall spacers 106 formed on side surfaces of the gate electrode 105, extension regions 107 formed on opposite side regions of the fin-shaped semiconductor regions 103a to 103d sandwiching the gate electrode 105 therebetween, and source-drain regions 117 formed on opposite side regions of the fin-shaped semiconductor regions 103a to 103d sandwiching the gate electrode 105 and the insulative sidewall spacer 106 therebetween. The fin-shaped semiconductor regions 103a to 103d are placed on the insulating layer 102 so as to be arranged at regular intervals in the gate width direction. The gate electrode 105 is formed so as to extend across the fin-shaped semiconductor regions 103a to 103d in the gate width direction. The extension region 107 includes a first impurity region 107a formed in an upper portion of each of the fin-shaped semiconductor regions 103a to 103b, and a second impurity region 107b formed in a side portion of each of the fin-shaped semiconductor regions 103a to 103b. The source-drain region 117 includes a third impurity region 117a formed in an upper portion of each of the fin-shaped semiconductor regions 103a to 103b, and a fourth impurity region 117b formed in a side portion of each of the fin-shaped semiconductor regions 103a to 103b. Note that pocket regions are not described herein or shown in the figure.
FIGS. 28A-28D are cross-sectional views showing step by step a conventional method for producing a semiconductor device. Note that FIGS. 28A-28D correspond to the cross-sectional structure taken along line C-C in FIG. 27A. In FIGS. 28A-28D, like elements to those shown in FIGS. 27A-27D are denoted by like reference numerals and will not be described redundantly.
First, as shown in FIG. 28A, there is provided an SOI (silicon on insulator) substrate, in which the insulating layer 102 made of silicon oxide is provided on the supporting substrate 101 made of silicon, and a semiconductor layer made of silicon is provided on the insulating layer 102. Then, the semiconductor layer is patterned to form the fin-shaped semiconductor region 103b to be the active region.
Then, as shown in FIG. 28B, the gate insulating film 104 is formed on the surface of the fin-shaped semiconductor region 103b, after which a polysilicon film 105A is formed across the entire surface of the supporting substrate 101.
Then, as shown in FIG. 28C, the polysilicon film 105A and the gate insulating film 104 are etched successively to form the gate electrode 105 on the fin-shaped semiconductor region 103b with the gate insulating film 104b interposed therebetween. Then, using the gate electrode 105 as a mask, the semiconductor region 103b is ion-implanted with an impurity to form the extension region 107 and the pocket region (not shown).
Then, as shown in FIG. 28D, an insulating film is formed across the entire surface of the supporting substrate 101, and then the insulating film is etched back by using anisotropic dry etching to thereby form the insulative sidewall spacer 106 on the side surface of the gate electrode 105. Then, using the gate electrode 105 and the side wall 106 as a mask, the semiconductor region 103b is ion-implanted with an impurity to form the source-drain region 117.
Through the steps described above, it is possible to obtain a fin-shaped MISFET (metal insulator semiconductor field effect transistor) having the gate electrode 105 formed on the fin-shaped semiconductor region 103b with the gate insulating film 104b interposed therebetween.
In recent years, it has been drawing attention to use a plasma doping method in order to conformally dope the upper surface and the side surface of a fin-shaped semiconductor region. For example, a pulsed DC plasma technique has been proposed in the art (Non-Patent Document 1) as a plasma doping method used for conformal doping. This is a method in which a plasma is generated on and off, and has an advantage in that etching is unlikely to occur. However, if the method is used for doping a fin-shaped semiconductor region, the specific resistance of the side surface of the semiconductor region will be larger than that of the upper surface of the semiconductor region.
Note that in addition to the pulsed DC plasma technique of Non-Patent Document 1, plasma doping methods include a method disclosed in Patent Document 2 as a representative method. Patent Document 2 proposes a technique using an inductively coupled plasma (ICP) method. This is a method desirably capable of uniformly doping into the surface of a large substrate such as a wafer having a diameter of 300 mm, for example, by employing a longer time region (doping time) than that used in a pulsed DC plasma method.
Patent Document 3 discloses a plasma doping method for conformally doping the trench side surface. Note however that this is a technique for doping only the trench side surface, and it is not an object of the technique to dope the upper surface and the side surface of a fin-shaped semiconductor region. That is, with a method doping only the side surface as disclosed in Patent Document 3, doping is performed while masking the upper surface, thus failing to realize effects of the present invention to be described later, such as the realization of conformal doping on the upper surface and the side surface, and the prevention of chipping of the upper corner of a fin-shaped semiconductor region.    Patent Document 1: Japanese Published Patent Application No. 2006-196821    Patent Document 2: International Publication WO2006/064772    Patent Document 3: Japanese Published Patent Application No. H01-295416    Non-Patent Document 1: D. Lenoble, et al., Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions, 2006 Symposium on VLSI Technology Digest of Technical Papers, p. 212